Applicable Models
**AOTD ** LATT
**AOTD ** LBTT
**AOTG ** LATT
Purpose
This procedure details the method for testing Power Factor Correction (PFC) PCBs used in Fujitsu inverter systems.
The PFC circuit improves power factor by converting AC input to stable high-voltage DC output.
A failed PFC PCB may cause circuit breaker tripping immediately upon system power-up
PFC testing (1)
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Symptoms of Failure
Breaker trips when energized.
No DC bus voltage detected.
Inverter board or compressor fails to start.
Test Equipment
Digital multimeter set to diode test mode.
Ensure power is isolated and capacitors are fully discharged before testing.
Testing Overview
Testing is similar to IPM (Intelligent Power Module) diagnostics, though choke coils in the PFC circuit slightly affect readings
PFC testing (1)
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Refer to the PCB diagram on page 1, which identifies test terminals:
TM504 – Positive terminal (Orange)
TM505 – Negative terminal (Purple)
Additional test points TM500 – TM503 for diode path evaluation
PFC testing (1)
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Test Points and Expected Readings
| Red Lead | Black Lead | Expected Reading (V) |
|---|---|---|
| TM504 | TM500 | O/L |
| TM504 | TM501 | O/L |
| TM504 | TM502 | O/L |
| TM505 | TM500 | 0.4 |
| TM505 | TM501 | 0.4 |
| TM505 | TM502 | 0.4 |
| TM501 | TM504 | 0.4 |
| TM502 | TM504 | 0.4 |
| TM503 | TM504 | 0.4 |
| TM502 | TM505 | O/L |
| TM503 | TM505 | O/L |
Acceptable range: 0.35 – 0.45 V on diode path readings.
Failed board indication: 0.0 V on any test point = shorted PFC circuit
PFC testing (1)
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Key Notes
Always test with power off and capacitors discharged.
Normal diode voltage drops confirm PFC transistor integrity.
Abnormal or open readings (O/L on both directions) indicate component failure or open circuit.
Technician Tip
If the PFC board fails testing, it should be replaced as a complete assembly.
Do not attempt component-level repair due to potential high-voltage residual energy and calibration risks.